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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded / System Software,Embedded, VLSI |
| EmploymentType | Full-time |
Job ID: JR0148845Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireAnalog Design Engineer (PLL IP)Job DescriptionYou will be joining an expanding analog/mixed-signal PLL team involved in design and development on cutting-edge Intel and external foundry process development nodes.Your responsibilities will include but not be limited to:The candidate should have experience in Analog and Mixed Signal Design with focus on PLLs and clocking circuits.Strong fundamentals of CMOS design, passive RC circuits, switched cap circuits are a must for this role.The various task involves, circuit design, validation, mixed signal validation, and reliability validation.Exposure to PLL designs (either Charge-Pump based or ADPLLs or both, Fractional-N PLLs, spread-spectrum PLLs, etc.)High speed digital circuit design and analysis with timing and flow closure.Digitally assisted analog circuit and techniques.The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL.Good knowledge of control systems, band gaps, bias, op-amps, LDOs, feedback and compensation techniques.Experience in LC VCO/DCO design. Good exposure to performance parameters of VCO as well as complete PLL architecture.QualificationsCandidate should possess at least a Master of Science degree in Electrical Engineering or equivalent. Strong academic background required in CMOS semiconductor device physics and silicon processing. Relevant coursework in CMOS digital, analog, and I/O circuit design Knowledge of transistor-level circuit simulation tools such as SPICE The following preferred qualifications would be an added advantage: 5-10 years of experience in Circuit Design. Familiarity with CMOS transistor and semiconductor device layout methods.Experience using custom design environments such as Cadence design automation tools (ADS, Analog Artist, or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0148845Bangalore,
Keyskills :
drawingautocaddraftingmodelingcadmixed signal designdigital circuit designintegrated development environmentsmixed signalsignal designcircuit designautomation toolsdesign automation