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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
Documenting learnings, results and process developments for other engineers to leverage.Exploring, developing and documenting new methods to characterize PHY circuit behavior in simulation and/or lab environments.Working with the silicon PHY development team to learn transmitter and receiver architectures in order to collaborate to fine-tune the IO equalization features for a given application.Working with signal integrity teams to develop best known behavioral modeling methods.The applicant should possess demonstrated ability to model and simulate the pad-pad interconnect on multi GHz differential IO links. Prior experience in designing DDR3/4, LPDDR3/4, HBM, PCIE3/4, 10KR, USB, SATA, 10KR busses are highly valued.Knowledgeable of signal integrity concepts such as: propagation, losses, parasitics, reflections, xtalk, ground bounce, power delivery and bypassing techniques for power/ground noise reduction, termination techniques for reflection noise control, on chip crosstalk, I/O buffer modeling, and the understanding of basic transistor circuitsExperience with Frequency domain analysis for signaling and power delivery as well as understanding the sources of jitter and reduction techniquesStrong analog background and Spice experience with strong programming skills using PERL and MATLAB -Working knowledge with lab equipment such as with oscilloscopes, Time Domain Reflectometers (TDR), and skew/jitter measurementsGood oral and written communication skillsTeam player, willing to take on a variety of projects,
Keyskills :
drawingautocaddraftingmodelingcadnoise controlpower deliverydomain analysisnoise reductionsignal integritycommercial models