DFT Engineer

Job Description

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.What you do at AMD changes everythingAt AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, Immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.JOB TITLE HERETHE ROLE:

• As a member of the SCBU SoC DFT Team, the successful candidate will own the DFT micro-architecture and RTL implementation using Verilog/System Verilog for the next gen of AMD SCBU SoCs.)
• Position includes test creation/development, characterization, data analysis, and silicon debug of DFT Scan/ATPG test in leading edge process technologies. AMDs environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology!

THE PERSON:

• A successful person in this role would be able to work in a collaborative team environment working with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects
• Strong self-driving ability, Should have excellent communication skills (both written and oral)
• Strong problem-solving skills

KEY RESPONSIBILITIES:

• Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level
• Working closely with the ATPG team for coverage support, with the DV team on helping debugging and root-causing the test failures and with the PD team on DFT timing closure

PREFERRED EXPERIENCE:

• Experience in DFT architecture for complex chips
• Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration
• Proficient in doing basic unit-level verification using simulations.
• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
• Must have experience with integration of various IPs into complex SOCs.
• Exposure to Static timing analysis & Timing closure is required.
• Any prior experience with microprocessor designs is a plus.
• Scan/ATPG patterns & test flows development, debug, test and characterization
• Pre-Silicon test planning & validation, Engagement with Design
• Post Silicon Bring up of test patterns leading to optimization for mass production enablement
• Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
• Optimization of test flows for increased quality and cost improvement
• Analysis of part failures leading to test coverage and yield improvement
• Analysis of characterization data across PVT
• Excellent hands-on debug skills and scripting skills are critical.
• Must have good communication skills and the ability to work in a worldwide team environment.
• Knowledge & experience of low power concepts, clock gating, power gating is a plus
• Experience with post-silicon bring up is a plus

ACADEMIC CREDENTIALS:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

• 4+ years experience in RTL design

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Keyskills :
timing closurequality checkscanchanging the worldstatic timing analysisdata analysistest planningtest coveragedftatpgcoresilicon