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Eng Integration & Yield Defect Engineer

0.00 to 3.00 Years   Bangalore   11 Jan, 2021
GLOBALFOUNDRIES
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

* Company DescriptionGLOBALFOUNDRIES is the world s leading specialty foundry. We deliver differentiated feature-rich solutions that enable our clients to develop innovative products for high-growth market segments. GF provides a broad range of platforms and features with a unique mix of design, development and fabrication services. With an at-scale manufacturing footprint spanning three continents, GF has the flexibility and agility to meet the dynamic needs of clients across the globe. We are changing the industry that s changing the world. Job Title: Defect Engineer (Contamination Free Manufacturing or Defect Metrology)This position is for a Senior Defect Engineer in GLOBALFOUNDRIES India center at Bangalore, supporting 200 and 300mm wafer fabs in US, Singapore, and Germany. The candidate will be primarily responsible to provide accurate analysis of defects identified during semiconductor manufacturing processes. Specific Responsibilities

  • Analyze in-line defect data from inspection and SEM review tools
  • Troubleshoot and shutdown the affected process tools based on data analysis
  • Perform lot disposition for CFM YDD inspected lots
  • Ensure OOC lots are on hold for troubleshooting
  • Support Modules, Process Integration group and TD group for inline defect support
  • To check daily YDD scan map
  • Overall WIP Control Management
  • Able to work with module for inline OOC follow up and root cause investigation
  • Able to chair meeting independently for inline excursion
  • Able to do defect source analysis base on defect images and wafer map signature
  • Able to do data analysis by using tool commonality, DSA scan, DOE split scan
  • Able to monitor inline SPC defect trend charts to prevent baseline defect performance drift or inline excursion
  • Able drive chronic defect improvement with different modules
  • Always work as a team and be flexible and resourceful to achieve the best result on a given timeline
  • Clear reporting and communication of issues to home Fab teams on a daily basis
  • Must be flexible in job assignment and ready to work on weekend shifts on a rotational basis as required by the business
, * Required Qualifications
  • B.E./B.Tech./M.Sc with 0-3 years of relevant experience in Electrical (Microelectronics)/ Electronics Engineering, Materials Science or Physics
  • Good understanding of basic concepts in Physics, Chemistry, Electronics and preferably Semiconductor processing and technology
  • Basic knowledge of Statistics and SPC & DOE methodologies is preferred
  • Working experience in CMOS process and process module/equipment (200mm/300mm) are strongly desired
  • Excellent verbal and written English communication skills
  • Strong team player with the ability to work well within a global team
  • Organized with a high attention to detail and on-time delivery of work assigned

Keyskills :
continuous improvement facilitationroot causedata analysissource analysisprocess integrationcommunication skillselectronics engineeringsemiconductor manufacturingsemspcdsa

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