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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded / System Software,General / Other Software |
| EmploymentType | Full-time |
Job ID: JR0163223Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireFull Chip Timing EngineerJob DescriptionIn this position you will be responsible for all aspects of STA and timing closure activities of Intel SoCs in lower technology nodes Your tasks will include but not limited to Design and Architecture understanding Interaction with FEDFT Verification teams Clocking Constraints development ACIO Timing Understanding on synchronous and asynchronous paths Clock domain crossing issues Understanding and debugging extraction issues Deciding timing signoff modes and corners Design margins Hierarchical timing including IO budgeting for partitions Drive the designs to timing closure interacting supporting synthesis and APR team during timing closure cycle timing ECOs Timing model build Timing signoff and quality checksYou will also be part of debug troubleshoots for a wide variety of tasks up to and including difficult critical design issues and proactive intervention as requiredQualificationsB Tech or M Tech in Electrical Electronics Engineering with 10 years of experienceMasters Degree in Electrical or Electronics Engineering with VLSI or Microelectronics specialization with 10 years of experience in STAKey SkillsIn depth knowledge with hands on experience with the overall silicon implementation flows and methodologies such a STA Synthesis Clocking is required Good understanding and exposure of overall Timing closure cycle in SoCGood scripting skills in TCL Perl Shell Expertise in STA signoff tools PT ETSSkill in Synopsys tools PT DC and exposure to ICC will be an added advantageSolid technical and good communication skillsInside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intels leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0163223Bangalore,
Keyskills :
timing closuresynopsys toolsclient developmentbehavioral trainingelectronics engineeringstaiccvlsiperlecoscolordesigntimingclosuresiliconbusinessclockingtclipsintel