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| Job Location | Bangalore |
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| EmploymentType | Full-time |
Job ID: JR0166302Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireFull Chip Timing EngineerJob DescriptionOversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.QualificationsQualification: Education: B.Tech. or M.Tech. in Electrical and-or Electronics Engineering with 4-12 years of experience Key Skills: In-depth knowledge and hands-on experience with the overall silicon implementation flows and methodologies such a STA, Synthesis, Clocking is required. Good understanding and exposure of overall Timing closure cycle in SoC. Good scripting skills in TCL-Perl-Shell. Expertise in STA signoff tools (PT-ETS). Skill in Synopsys tools (PT-DC) and exposure to ICC will be an added advantage. Solid understanding of process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. Solid technical and good communication skills.Inside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intels leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0166302Bangalore,
Keyskills :
design flowlogic designtiming closuresynopsys toolsclient developmentbehavioral trainingarchitectural designelectronics engineeringtestscolordesignvendortimingclosureFull Chip Timing Engineer