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MTS Silicon Design Engineer

10.00 to 12.00 Years   Bangalore   24 Sep, 2021
Advanced Micro Devices, Inc
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryTelecom / ISP
Functional AreaService / Installation / Repair
EmploymentTypeFull-time

Job Description

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.Responsibility:

  1. Responsibility:
  2. Work closely with SOC Architecture team for SOC clocks statistical timing target goals.
  3. Responsible for merging the IP level timing constraint to SOC level, maintain all SOC level clocks definition and exceptions.
  4. Responsible for full timing constraints delivery to Physical Design, timing constraints quality, check timing result, and update timing result.
  5. Responsible for working with Physical design and IP teams to close timing by fix timing constraint issues
  6. Responsible for SOC level timing constraints signoff and work closely with IP for timing constraints review and signoff.
  7. Collaborate with IP team to make sure the proper constraints are integrated and feedback any issues from SOC level.
  8. Understanding clock design requirements and make sure they are correctly setup in SDC.
  9. Requirement:
  10. BS or MS in Electrical Engineering or related technical areas
  11. > 10 years working experience on SOC Implementation and Tapeout
  12. Have strong knowledge with digital design timing signoff methodology.
  13. Familiar with STA(static timing analysis) methodology
  14. Familiar with timing target definition methodology
  15. Familiar with SOC architecture and design knowledge, such as Serdes, AXI buses, source synchronous and test design.
  16. Strong commitment to schedule and quality of the SDC delivery in project s each milestone.
  17. Have experience on complex SOC full chip timing constraints delivery and timing quality check
  18. Have good communication skills and be able to work both independently and in a team, can co-work with IP and PD team on the timing closure .
  19. Can lead a small team , 2~4 people , to deliver the tasks.
  20. Familiar with EDA tools: GCA (Galaxy Constraint Analyzer) , PT(Prime Time) , Fishtail
  21. Good teamwork and leadership skills
  22. Good script development skills
,

Keyskills :
working experiencedigital designdrawingmodelingcadtechnical compliancetiming closuredraftingchanging the worldautocadcommunication skillsphysical design

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