Physical Design Engineer

Job Description

Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePhysical Design EngineerJob DescriptionCreates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.QualificationsJob RequirementIn this position you will be responsible for all aspects of NetlisttoGDSII closure activities of Intels SoCs in lower technology nodes Your tasks will include but not limited toDrive and own handson design convergence and quality for large blocks clusters from RTL to GDS Synthesis Place and Route Timing Physical Verification etcWork extensively with implementation and RTL teams to help optimizeconverge the designs and drive PPA improvementsDrive design methodologies and key functional areas providing technical leadership and guidanceWell versed with the Block and Full chip level timing closure STA methodologies ECO generation and predictable convergence Well versed with parasitic extraction LVSDRC and other Physical verification checksEnsure cross teams communications with Logic and Arch Teams and also with FullChip Timing CAD and Integration TeamsInfluence tools flows and overall RTL to GDS2 physical design methodology with a data driven approachQualificationsEducation BTech or MTech in ElectricalElectronics Engineering with 412 years of experienceKey skills Experience in physical implementation with multiple design cycles in ASIC flow is required Strong knowledge of synthesis physical design STA and verification flows methodology and knowledge of all aspects of physical design is required Knowledge of low power flow power gating multiVt flow power supply management etc Experienced in industry standard tools such as Synopsys ICC ICC2 PrimeTime ICV Mentor Calibre and Calibre DRV is required Experience in scripting languages preferably Perl Python Tcl etcis preferred Excellent oral and written communication skillsInside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intels leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.,

Keyskills :
floor planningdrcroutingverificationintegrated development environmentspower flowchip designfloor planspower supplyrc extractiontiming closurephysical design