| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Oil & Gas Jobs |
| Banking Jobs |
| Construction Jobs |
| Top Management Jobs |
| IT - Software Jobs |
| Medical Healthcare Jobs |
| Purchase / Logistics Jobs |
| Sales |
| Ajax Jobs |
| Designing Jobs |
| ASP .NET Jobs |
| Java Jobs |
| MySQL Jobs |
| Sap hr Jobs |
| Software Testing Jobs |
| Html Jobs |
| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Network / System Administration |
| EmploymentType | Full-time |
Creates bottomsup elements of chip design including but not limited to FET cell and blocklevel custom layouts FUBlevel floor plans abstract view generation RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction static timing wire load models clock generation customer polygon editing autoplace and route algorithms floor planning fullchip assembly packaging and verification Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention Schedules staffs executes and verifies complex chips development and execution of project methodologies andor flow developments Requires expansive knowledge and practical application of methodologies and physical designQualificationsJob Requirement In this position you will be responsible for all aspects of NetlisttoGDSII closure activities of Intels SoCs in lower technology nodes Your tasks will include but not limited to Drive and own handson design convergence and quality for large blocks clusters from RTL to GDS Synthesis Place and Route Timing Physical Verification etc Work extensively with implementation and RTL teams to help optimizeconverge the designs and drive PPA improvements Drive design methodologies and key functional areas providing technical leadership and guidance Well versed with the Block and Full chip level timing closure STA methodologies ECO generation and predictable convergence Well versed with parasitic extraction LVSDRC and other Physical verification checks Ensure cross teams communications with Logic and Arch Teams and also with FullChip Timing CAD and Integration Teams Influence tools flows and overall RTL to GDS2 physical design methodology with a data driven approach Qualifications Education BTech or MTech in ElectricalElectronics Engineering with 412 years of experience Key skills Experience in physical implementation with multiple design cycles in ASIC flow is required Strong knowledge of synthesis physical design STA and verification flows methodology and knowledge of all aspects of physical design is required Knowledge of low power flow power gating multiVt flow power supply management etc Experienced in industry standard tools such as Synopsys ICC ICC2 PrimeTime ICV Mentor Calibre and Calibre DRV is required Experience in scripting languages preferably Perl Python Tcl etcis preferred Excellent oral and written communication skillsInside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intels leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.,
Keyskills :
floor planningdrcroutingverificationintegrated development environmentspower flowchip designfloor planspower supplyrc extraction