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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Network / System Administration |
| EmploymentType | Full-time |
As an integral part of Intel, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.Roles and responsibilitiesWe are looking for physical design methodology engineer to drive the place and route, PPA optimization methodologies for the IFS team. The responsibilities includes but not limited to automation of advanced place and route methodologies that leverage the Intel foundry technology and deliver the best in class PPA targets for the internal and external designs of IFS.Right Candidate will bring-in 12+ years of in-depth technical experience in design and methodology of place and route stages from RTL2GDSII on high-end SOC TO on Chips Such as Server CPUs/SOCs, Graphics SOCs or SOCs in AI Space on 10nm, 7nm or 5nm or other advanced foundry processes. Candidate should have in-depth understanding of PD concepts working on advanced EDA tools like Genus, Innovus, Fusion Compiler, ICC2 etc. along with hands on expertise in enabling tape-outs on advanced process nodes. The candidate should have track record of being part of 3 or more tape-outs in Advanced process technologies and rich experience in working complex PPA and low power problems in design convergence. The candidate should have worked on advanced low power implementation techniques using hierarchical UPF based implementation. The candidate must be an expert problem solver and with agile/fast moving mindset and customer oriented. Proactive attitude to build a correct by construction and best in class design implementation flows, planned and organized work style and excellent teamwork needed.QualificationsBachelors/Masters degree in Electronics/Computer Science required with 5+ years experience,
Keyskills :
continuous improvement facilitationeda toolssupply chainphysical designconnected devicesprocess developmentbehavioral trainingsemiconductor process