Pre-Si Valid/Verif Engineer

Job Description

Job ID: JRhidden_mobileJob Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePre-Si Valid/Verif Engineer Job Description We are seeking highly motivated, energetic, team-oriented engineer willing to take the challenge of delivering Pre-Silicon validation of industry leading IPs that are used across various SOCs in Intel. In this position, you will participate in the development and validation of various Hard-IPs for various process technologies. You will focus on executing to pre-silicon validation plans as per the hard-IP/product release schedule and deliverables, and carry out debug, report failures, report potential failures and help with root-causing the failures. You may also interface with other validation teams and will also work on improving existing processes and validation methodologies. You will be required to create verification test plans, drive/participate in discussions across various disciplines to get a clear understanding of requirements, develops the architecture and design of the verification environment in OVM/UVM for pre-silicon RTL verification, develops/run/debug tests in SystemVerilog, mentor other engineers in using the verification infrastructure and creating test benches. You may work on verification of block/cluster/IP level testing, actively review code created by fellow teammates, participate in functional coverage, code coverage reviews and provide/implement feedback. You should be able to support debugs on sub-system/SOC that use the IP provided. You should also be able to support post-silicon/platform failures related to the IP provided. You may be required to contribute to the development and maintenance of long-term design verification strategy. You should track progress of self/sub-team to achieve goals timely, provide indicators and guidance to management on issues and roadblocks on a timely basis and be able to work with teams across different geographies.Qualifications You should possess a Masters or Bachelors degree in Electrical/Electronics/Computer Engineering, with 3-8 years of relevant experience in the industry. Additional qualifications/skills include: Experience in developing high quality validation plans, collecting and analyzing the test results and being able to debug the failures to RTL/gate/schematic level Strong problem-solving and teamwork skills, and strong verbal and written communication skills Ability to produce results in a challenging, fast-paced, multi-site, multi-group environment Good working knowledge of HDLs and HVLs like VHDL, Verilog HDL, SystemVerilog is a must. Good working knowledge of either one or more of reuse methodologies like VMM/OVM/eRM/AVM/RVM, preferably UVM. Good understanding of IO design and validation methodologies, and electrical and system validation issues related to analog, digital, and mixed-signal circuits/IPs would be a big plus. Understanding of design-for-testability and design-for-reliability methodologies would be a big plus. Work experience with at least one other verification aspect like Performance modeling, Formal verification, Gate Level verification, Emulation, etc. would be an added advantage. Proficiency in scripting languages and utilities including Make, Perl, Python, etc. will be a bonus. Experience in mixed signal IP design verification is a plus with protocols such as PCI-Express, SATA, USB, Display I/O, MIPI, Ethernet, etc. and AMBA, JTAG, PIPE, etc. is desired. Should be able to contribute as IC or technically leading a group of team members as per requirementInside this Business Group IP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJRhidden_mobileBangaloreIP Engineering Group (IPG),

Keyskills :
io designverilog hdlmixed signalcode coverageproblem solvingrtl verificationcommercial modelsbehavioral trainingformal verificationdesign verification