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Principal Design Engineer

5.00 to 15.00 Years   Bangalore   12 Jun, 2022
Cadence Design
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Develop and lead development of major ASIC blocks and subsystems (in some cases involving FPGAs), from concept to productization including:o Balancing performance, area, power, and complexityo Interfacing to third-party IPo Working with physical design team on floor-planning and other physical issueso Determining and executing development, integration, bring-up and test plans.o Writing detailed complete internal specificationso Completing implementation in RTL and evaluating synthesis results for performance and costo Ensuring robust and complete timing constraints and evaluating STA results.o Working closely with verification teams during developmento Collaborating with firmware teams during specification and integrationo Working with system and design validation testing teams during bring-up and DVT phases.o Guiding diagnostic and test teams in recommendations to achieve appropriate fault isolation, and function and robustness tests Work in small dynamically evolving teams for subprojects involving internal and external resources. Mentor junior team membersDevelop a deep understanding of the emulation system to contribute to design improvements, support product development teams, and provide ongoing debug and analysis support of the ASIC designQualifications 5-15 years of relevant experience. Degree in Electrical or Computer Engineering, graduate level or compensating experience. Proven success in development of complex ASIC, FPGAs and products. Demonstrated capability to design major blocks involving ASIC, IPs, logic, and FPGAs. Excellent logic developer in Verilog / SystemVerilog. Aware of ASIC design flow. Experience with frontend design tools (Xcelium/Incisive, LINT tools, Genus/Design-Compiler, STA with Tempus/PrimeTime, power analysis); expert in at least one of these areas. Exposure to backend tools a plus. Relevant experience in some major IPs and protocols, such as SERDES, PCIe and DDR4, and ASIC IP integration in general. Expert in at least one such area. Understands DFT, BIST, other DFx methologies. Great scripting skills (e.g. Python, Bash, etc.) Familiarity with verification methodologies and emulation or prototyping experience helpful. Excellent problem-solving and debug skills. Comfortable researching IP, firmware, compiler and systems domains as needed. Ability to work cross-functionally. Ability to quickly multi-task among many small projects. Does not wish to be confined to a small focused role. Driven to understand the big picture. Can easily switch gears and take on new and diverse tasks. Energetic. Self-driven. Good communication, organization, analytical, presentation and people skills. We re doing work that matters. Help us solve what others can t. ,

Keyskills :
lightingestimation3d modellingahuauditingfront endasic designgraduate levelphysical designproblem solvingfault isolationlead development

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