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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Company Profile: Western Digital Corporation is the world s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions. Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess.Innovating at the Boundaries of Technology: Whether in your pocket, home, car, or the cloud, it s likely Western Digital is with you every step of the way. Its a responsibility we dont take lightly. Thats why we are always at the cusp of innovation, pushing the boundaries of technology to make what you thought was once impossible, possible.We deliver the possibilities of data. YOU define what s possible. The next big thing in data is you! Shape the future & define whats possible. Come shape the future with us. For more information about us, please visitJob-Title: STA/Timing closureExperience: 8-18 yearsResponsibilities: In this position, the individual will be responsible for complete ownership of full chip Synthesis /STA environment for low power, high performance designs, development-debug of interface and core side constraints, clock tree analysis and assisting full chip timing convergence and timing closure.Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments.He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.The individual will influence next generation synthesis and physical design implementation capability to meet the demands of the ASIC design road map.Ability to work with minimal supervision and drive to exceed expectations is a plus.Hands on direct experience in Synthesis with emphasis on STA and Low Power design. Proficiency in understanding and writing Verilog, System Verilog RTL, STA closure and experience in PERL/TCL/Shell scripting is a must.The individual must have proven hands on experience on multiple low power hierarchical and flat ASICs at 28/16nm designs.Expertise in Design Compiler is a must. Experience with DFT Compiler, RTL Compiler and Conformal is a PLUS.Good verbal and written communication skills are required.Work-Location : BangaloreLegal Disclaimer WD is an Equal Opportunity Employer and Prohibits Discrimination and Harassment of Any Kind: WD is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. All employment decisions at WD are based on business needs, job requirements and individual qualifications, without regard to race, colour, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation, family, parental status, or any other status protected by the laws or regulations in the locations where we operate,
Keyskills :
ppapproduct developmentasic designrtl compilerdft compilersystem verilogphysical designdesign compilercommunication skillswritten communicationintegration strategiesedadftrtl