Principal Engineer (PCIe Controller stack) - Data Center IP Development

Job Description

Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePrincipal Engineer (PCIe Controller stack) - Data Center IP DevelopmentJob DescriptionPrincipal Engineers at Intel are active technical leaders inside and outside the company. Activities include driving key technologies besides participation in major industry and academic conferences, voting membership in international standards committees, generation of patents and technical papers. Responsible for working with standards bodies in high speed serial IO-Technology controllers domain (like PCIe, CXL and/or adjacent standards) with goal of of Defining and Driving state of the art digital controller IP-stack roadmap and solutions (including MAC, Link Layer, transport layer) with best in class KPIs. Responsibilities would include owning the end to end IP stack development from architecture concept to production quality IP including (but not limited to) defining roadmap, RTL microarchitecture, pipelines, review IP verification strategies & plans , mentor senior RTL designers on execution & best in class quality, support post silicon/emulation teams for any debug etc.QualificationsYou must possess a Bachelor/Masters/Ph.d degree in electronics/electrical/communication/VLSI/Microelectronics and/or related engineering/technology with experience in the range of 18 to 28 years in defining specifications/architecture & execution of RTL/Logic design of IPs in high speed serial IO domain (PCIe/CXL etc) . Publications and patents in relevant fields would be an added advantage. Below are some of the specific expectations for this role - Expertise & deep understanding of PCIe and/or CXL standards and prior experience on PCIe and/or CXL IPs execution is a must. - Expertise in complex digital IP microarchitecture design with prior experience in complex pipeline /data-path optimizations using system Verilog. - Hands-on expertise in highspeed digital IP with multiple clock domain, power plan designs - Familiarity with overall silicon development cycle from concept to PRQ including DFT/DFD/Post Silicon debug support, HW/SW partitioning is desired. - Expertise with Verilog, system Verilog, C, C++, Perl languages - Ability to clearly express technical concepts in verbal and written form - Innovative thinking, problem solving, good communication skills, self-discipline and results orientation are critical soft-skills needed - Good hands-on knowledge on industry standard EDA tools & HDLs - Must be a extremely good team player and should be able to work across organization boundaries and domains. - Must possess excellent communication skills & should be able to participate and represent the given IO technology at various international forums (inside and outside) and executive levels.Inside this Business GroupThe Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.,

Keyskills :
javalinuxjavascriptframeworkeda toolsdata centersoft skillssystem verilogbehavioral traininginternational standardsmacartedartl