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Principal Engineer - STA

5.00 to 10.00 Years   Bangalore   14 Sep, 2021
Marvell India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

About MarvellAt Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world s leading technology companies for 25 years, we move, store, process and secure the world s data with semiconductor solutions designed for our customers current needs and future ambitions. Through a process of deep collaboration and transparency, we re ultimately changing the way tomorrow s enterprise, cloud, automotive, and carrier architectures transform for the better.The data infrastructure that our customers build has never been more critical to our global economy. It s what s keeping the world connected, businesses running, and information flowing. If you re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The OpportunityThis position is with central cad and design services (CCDS) physical design (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in RTL to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation for all internal business units. We are looking for strong technical leaders having Full-Chip Synthesis, Static Timing Analysis and Physical Design experience on hierarchical designs using industry standard tools.Marvell is looking for a Timing lead who will work with global teams in handling Timing sign off for multi-million hierarchical designs with latest technology nodes (16/5 nm). To mentor and provide technical guidance to a team of junior engineers, reviewing designs for successful execution of the program.

  • B-Tech/M-Tech candidate with 10 years of hands-on experience and leadership in full-chip STA/Synthesis. Should have played a Timing lead role with 5 years experience in handling Timing sign off for multi-million hierarchical designs.
  • Should have hands on experience constraints development including third party IP s, budgeting and driving the timing closure for block, Subsystem as well as chip level.
  • Candidate should have excellent problem-solving skills in timing domain, should be well versed with scripting language PERL/TCL/AWK/Shell.
  • Candidate should have experience in working with global teams as a timing lead handling interaction with all stake holders, driving technical deliverables/dependencies across the design cycle (DFT/PD/FE/Power)
  • Candidate should possess excellent inter-personal skills with experience in providing mentorship to junior engineers, reviewing designs, and providing technical guidance.
The PerksWith competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page.Your FutureMarvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.,

Keyskills :
javascriptframeworkrtlproblem solvingstatic timing analysistiming closurecadjavalinuxphysical designtiming analysisgdsglobal teamsinterpersonal skillsexcel

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