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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.The Successful Candidate will Work with Best In Class Memory Design Team at Broadcom in Advanced Technology Nodes.JD for Staff Engineer:1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF Technologies2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.6) Logic simulations and detailed timing analysis of key paths in high speed memory design.7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.Skill Sets/Prerequisites1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits2) Experience in Designing and driving one or many Memory Compilers Specifications to final release 3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc7) Experience in Skill/Perl/Python Scripting is a strong plus 8) Experience in Understanding the layout design issues in sub nanometer regime is a must. 9. Expertise in Understanding Memory DFT is a Plus.10. Masters with 6-7 Years Experience or B.Tech with 8-10 years experience.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.,
Keyskills :
timing analysisqualityhspicemarketinglayout designcustomer relationsmargin analysisdfthsimcoloryieldtimingcircuit designsramvalidationcmosdesignstatistical analysisrail