SD (Physical Design) Engineer

Job Description

Job ID: JR*******Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSD (Physical Design) EngineerJob DescriptionXeon Server Solution (XSS) group in Intel is responsible for delivering complex Servers SoC catering to high bandwidth memory requirements for Data- center and cloud applications. In this position, candidate will be responsible for Netlist-to-GDSII (APR) closure activities for mega partitions and subsystems of Intels SoCs in lower technology nodes. Your tasks will include but not limited to: Drive and own hands-on design convergence and quality for large blocks, clusters from RTL to GDS [Synthesis, Place and Route, CTS, Timing, Physical Verification etc]. Work extensively with implementation and RTL teams to help optimize/converge the designs and drive PPA improvements Well versed with the Block and timing closure (STA) methodologies, ECO (timing, functional) generation and predictable convergence. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks Ensure cross teams communications with RTL Teams and also with Full-Chip Timing, CAD and Integration Teams Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approachQualifications Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 6+ years of experience Key skills Experience in physical implementation with multiple design cycles in ASIC flow is required. Strong knowledge of synthesis, physical design, STA and verification flows, methodology and knowledge of all aspects of physical design is required. Experience in 10nm or below technologies. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Experience in industry standard tools such as, Synopsys ICC2/Fusion compiler, Innovus, PrimeTime, ICV, Mentor Calibre, and Calibre DRV is required. Experience in scripting languages, preferably Perl, Python, Tcl, etc.is preferred Excellent oral and written communication skills.Inside this Business GroupXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOCs and critical IPs sustain Intels Xeon and 5G networking roadmap.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR*******BangaloreXeon Engineering Group (XEG), Job ID: JR0196028Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSD (Physical Design) EngineerJob DescriptionXeon Server Solution (XSS) group in Intel is responsible for delivering complex Servers SoC catering to high bandwidth memory requirements for Data- center and cloud applications. In this position, candidate will be responsible for Netlist-to-GDSII (APR) closure activities for mega partitions and subsystems of Intels SoCs in lower technology nodes. Your tasks will include but not limited to: Drive and own hands-on design convergence and quality for large blocks, clusters from RTL to GDS [Synthesis, Place and Route, CTS, Timing, Physical Verification etc]. Work extensively with implementation and RTL teams to help optimize/converge the designs and drive PPA improvements Well versed with the Block and timing closure (STA) methodologies, ECO (timing, functional) generation and predictable convergence. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks Ensure cross teams communications with RTL Teams and also with Full-Chip Timing, CAD and Integration Teams Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approachQualifications Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 6+ years of experience Key skills Experience in physical implementation with multiple design cycles in ASIC flow is required. Strong knowledge of synthesis, physical design, STA and verification flows, methodology and knowledge of all aspects of physical design is required. Experience in 10nm or below technologies. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Experience in industry standard tools such as, Synopsys ICC2/Fusion compiler, Innovus, PrimeTime, ICV, Mentor Calibre, and Calibre DRV is required. Experience in scripting languages, preferably Perl, Python, Tcl, etc.is preferred Excellent oral and written communication skills.Inside this Business GroupXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOCs and critical IPs sustain Intels Xeon and 5G networking roadmap.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0196028BangaloreXeon Engineering Group (XEG),

Keyskills :
power flowpower supplytiming closurephysical designsupply managementbehavioral trainingparasitic extractionphysical verificationwritten communicationcadgdssocrtlstaecoppaperlcloudtclasic