Senior Engineer Logic Verification

Job Description

Job ID: JR*******Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations: Malaysia, Penang;US, California, Folsom;US, California, Santa ClaraJob Type: Experienced HireSenior Engineer Logic VerificationJob DescriptionThe IP Engineering Group (IPG) organization is responsible for developing leadership IPs that power-winning products for our customers and Intel. IPG develops a broad portfolio of IP, including standard cell libraries, memory compilers, network on chip, audio and sensing IP, analog IP, and both controllers and PHYs for serial and parallel IO IP such as DDR/LPDDR, PCIe, USB, and Serdes. The Customer Engineering Group (CEG) within IPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and internal/external customers in all phases of IP development (architecture, pre-silicon, post silicon execution, validation, and debug). CEG engineers will embody customer obsession by quickly resolving customer issues and providing hands on debug on a wide range of technical issues spanning all design domains (logic design, timing, physical integration, emulation, documentation, and customer training). Responsibilities for this candidate can include but are not limited to the following: Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests. Proactively engage customers to avoid issues by anticipating roadblocks and working with the customer and IP design team to take preventative action. Provide clear and direct answers to customer questions. Also work with IP design teams to ensure high quality documentation is available. Investigate, debug and disposition customer bugs/sightings in a responsive and timely manner. Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in SOC environment. This may involve travel to customer sites. Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug.QualificationsMinimum Qualification: Must have a BS or MS or PhD in EE/CS or a Related Field. Minimum 8+ years of experience in one or more of the following areas: IP or SOC Integration, logic design or verification or mixed-signal verification. Minimum 3 years of experience with at least one or more industry standard IO interfaces including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc. Either PHY or Controller experience is good. Desired Qualifications: Able to work independently with design team and customers to solve issues either remotely or onsite. Strong written and verbal communication skills are critical Good understanding of industry standard IO specifications. Good understanding of IP integration and design flow challenges within the context of subsystems and SOCs. Post silicon experience in electrical validation (EV), system validation (SV) or high-volume manufacturing (HVM) from a design, firmware or MRC perspective and familiarity with lab equipment will be a plus.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Other LocationsMalaysia, Penang;US, California, Folsom;US, California, Santa ClaraIntel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR*******BangaloreIP Engineering Group (IPG), Job ID: JR0196666Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations: Malaysia, Penang;US, California, Folsom;US, California, Santa ClaraJob Type: Experienced HireSenior Engineer Logic VerificationJob DescriptionThe IP Engineering Group (IPG) organization is responsible for developing leadership IPs that power-winning products for our customers and Intel. IPG develops a broad portfolio of IP, including standard cell libraries, memory compilers, network on chip, audio and sensing IP, analog IP, and both controllers and PHYs for serial and parallel IO IP such as DDR/LPDDR, PCIe, USB, and Serdes. The Customer Engineering Group (CEG) within IPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and internal/external customers in all phases of IP development (architecture, pre-silicon, post silicon execution, validation, and debug). CEG engineers will embody customer obsession by quickly resolving customer issues and providing hands on debug on a wide range of technical issues spanning all design domains (logic design, timing, physical integration, emulation, documentation, and customer training). Responsibilities for this candidate can include but are not limited to the following: Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests. Proactively engage customers to avoid issues by anticipating roadblocks and working with the customer and IP design team to take preventative action. Provide clear and direct answers to customer questions. Also work with IP design teams to ensure high quality documentation is available. Investigate, debug and disposition customer bugs/sightings in a responsive and timely manner. Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in SOC environment. This may involve travel to customer sites. Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug.QualificationsMinimum Qualification: Must have a BS or MS or PhD in EE/CS or a Related Field. Minimum 8+ years of experience in one or more of the following areas: IP or SOC Integration, logic design or verification or mixed-signal verification. Minimum 3 years of experience with at least one or more industry standard IO interfaces including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc. Either PHY or Controller experience is good. Desired Qualifications: Able to work independently with design team and customers to solve issues either remotely or onsite. Strong written and verbal communication skills are critical Good understanding of industry standard IO specifications. Good understanding of IP integration and design flow challenges within the context of subsystems and SOCs. Post silicon experience in electrical validation (EV), system validation (SV) or high-volume manufacturing (HVM) from a design, firmware or MRC perspective and familiarity with lab equipment will be a plus.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Other LocationsMalaysia, Penang;US, California, Folsom;US, California, Santa ClaraIntel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0196666BangaloreIP Engineering Group (IPG),

Keyskills :
safetycommissioningsiteinspectiontroubleshootingcontinuous improvement facilitationdesign flowlogic designstandard cellbehavioral trainingdesign verificationcommunication skillsverbal communication