Senior PD Engineer

Job Description

Microsofts hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon. Microsoft s hardware teams are also expanding into new technologies such as quantum computing! ResponsibilitiesMicrosoft s Cloud Compute Development Organization (CCDO) is seeking passionate, driven and intellectually curious engineers to join our pre-silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, custom IP and SOC designs that can perform complex and high-performance functions in the most efficient manner. This new team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems.In this high impact role on the team, you will be responsible to:
• Own and drive floorplanning and design planning for optimizing large sub-chips for Power, Performance and Area
• Own and drive execution from synthesis to place and route of large sub-chips and/or full chip through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
• Have close collaboration with RTL team to help drive and resolve design issues related to fullchip and block closure.
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Implement robust clock distribution solutions using appropriate methods that meet design requirements.
• Make good independent technical trade-offs between power, area, and timing (PPA).
• Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.
QualificationsRequired:
• BS/MS in Electrical or Computer Engineering
• 8+ years of experience in semiconductor design.
• Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Preferred:
• Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes.
• Excellent project management skills and ability to juggle multiple projects at once.
• Strong understanding of constraints generation, STA, timing optimization, and timing closure.
• In-depth understanding of design tradeoffs for power, performance, and area.
• Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
• Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Fusion Compiler, Innovus etc.
• Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise.
• Strong problem-solving and data analysis skills
• Strong automation skills using scripting languages such as Perl, TCL, or Python.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work., Microsoft s Cloud Compute Development Organization (CCDO) is seeking passionate, driven and intellectually curious engineers to join our pre-silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, custom IP and SOC designs that can perform complex and high-performance functions in the most efficient manner. This new team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems.In this high impact role on the team, you will be responsible to:
• Own and drive floorplanning and design planning for optimizing large sub-chips for Power, Performance and Area
• Own and drive execution from synthesis to place and route of large sub-chips and/or full chip through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
• Have close collaboration with RTL team to help drive and resolve design issues related to fullchip and block closure.
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Implement robust clock distribution solutions using appropriate methods that meet design requirements.
• Make good independent technical trade-offs between power, area, and timing (PPA).
• Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.

Keyskills :
design compilerproduct planningdata analysisphysical designproblem solving