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Senior Principal Engineer G5 - IP Design

18.00 to 0.00 Years   Bangalore   09 Oct, 2021
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other Software,Sales / BD
EmploymentTypeFull-time

Job Description

NXP SemiconductorsN.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020.Key Responsibilities

  • Own and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team.
  • Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation.
  • Architect and Design complex IP and Subsystems across a range of protocols required for Edge processing and Automotive Self Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.
  • Own, Lead an Drive IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules.
  • Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure Zero Defect designs and drive and mentor teams towards that.
  • Own and Drive global IP design methodologies across sites with global stakeholders.
Key Skills
  • Self starter with 18 years of experience to Architect and Design complex IP design / Sub-system with minimal supervision.
  • AI and Machine Learning, Processor Designs like RISC-V Core, Cache based subsystems.
  • Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing,
  • Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2.
  • Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces.
  • Experience in microcontroller architecture, bus protocols like AHB/AMBA,AXI.
  • Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C for hardware modeling.
  • Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage.
  • Have worked on Testbench and Testplan development closely with the verification team.
  • Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage.
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Keyskills :
proposal writingcable routingcathodic protectionmachine learningserial protocolsquality adherencesilicon validationglobal rdconnectivity solutions

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