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Senior Staff Physical Design Engineer - Full Chip EM/IR

8.00 to 10.00 Years   Bangalore   14 Sep, 2021
Marvell India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

About MarvellAt Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world s leading technology companies for 25 years, we move, store, process and secure the world s data with semiconductor solutions designed for our customers current needs and future ambitions. Through a process of deep collaboration and transparency, we re ultimately changing the way tomorrow s enterprise, cloud, automotive, and carrier architectures transform for the better.The data infrastructure that our customers build has never been more critical to our global economy. It s what s keeping the world connected, businesses running, and information flowing. If you re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The OpportunityThe infrastructure Processor Business Unit (IPBU) delivers hardware solutions in the networking space to various customers. All aspects of chip design from RTL design, DFT, verification and Physical Design is managed by teams across various sites around the world with close collaboration with each other.

  • As an EM/IR Engineer (FullChip), you will be part of our SOC PD team responsible for running/supporting/maintaining the EM/IR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
  • Experience in running FullChip EM/IR analysis is required.
  • Work with PD block owners in helping them take their blocks (custom, PnR) through the PNR flow and making sure all the blocks meet the EM/IR requirements.
  • Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools.
  • Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CPF).
  • BSEE or MS with 8 years of experience running an industry standard EDA tools for EM/IR
  • Experience in tape-outs of high performance SOC is required.
  • Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification.
  • Experience in EM/IR flows and methodologies at block and full chip level.
  • Knowledge of EM/IR limits to be set for lower technology nodes.
  • Experience in debugging EM/IR issues and providing solutions to fix these.
  • Knowledge of scripting languages such as Perl/TCL is required.
  • Diligent, detail-oriented, and should be able handle delegation of assignments efficiently.
  • Must possess effective communication skills, self-driven individual and a good team player.
The PerksWith competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page.Your FutureMarvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.,

Keyskills :
chip designfloor planningroutingeda toolsdrcphysical designtiming closurertl designverificationeffective communication skillshardware solutionsclock tree synthesis

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