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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded / System Software,General / Other Software |
| EmploymentType | Full-time |
Job ID: JR0178805Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSoC Design Engg - SDJob DescriptionThe candidate will be performing the Structural Design and Physical Design implementation tasks for a world-class SoC Team. The primary responsibility of this role is RTL2GDSII implementation of Block/IP/SubSystem in challenging lower Technology Nodes. The candidate will be required to implement the Design through Logic Synthesis, DFT Insertion, Floorplanning, Placement, CTS, Routing stages and will also be responsible for Sign-Off closure for various domains e.g. Power Integrity/IR/EM, DRC, LVS, DFM, Formal Verification. Static Timing Analysis (STA) and Xtalk closure tasks will be required as part of Physical Design Closure. The candidate will be responsible for delivering the high-quality designs in a time-bound TapeIn/TapeOut schedule and commitment on time to market.QualificationsBachelors/Masters in EC/EE with 4 to 5 years of experience in Structural design/Physical design domain. Skills Required :- RTL to GDSII Structural and Physical Design implementation and convergence of complex Blocks/IPs.- Good understanding of Timing Constraints, Logic and Physical Synthesis Techniques, and Methodologies.- Hands-on experience in handling High-Performance Design Synthesis, Complex Floor-Planning, Power Grid, Place, and Route.- Good proficiency in handling Static-Timing analysis and closure in Synthesis and Physical Design Domain.- In-Depth Knowledge and experience of Low power implementation, UPF, Multi-Voltage Design.- Experience in Power Integrity/IR/EM analysis, Physical verification DRC/LVS/DFM closure, Formal Verification Sign-Off.- Handling Implementation/Physical Design tasks independently ensuring quality schedule of deliverables.- Experience in implementing IP/SoC Subsystems is a plus.- Experience with scripting in Python, Perl, and/or TCL.- Should possess strong planning and problem-solving skills.- Must possess good communication skills and contribute as an Effective Team Player.Inside this Business GroupXeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0178805BangaloreXeon Performance Group (XPG),
Keyskills :
static timing analysisdata centermarket sharephysical designtiming analysislogic synthesisstructural designphysical synthesisformal verificationcommunication skillsphysical verificationdftsocrtldfm