SOC Design Engineer Lead

Job Description

Job ID: JR0151910Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSOC Design Engineer LeadJob DescriptionIn this position, you will be responsible for managing and working on all aspects of physical design activities of Intels SoCs in lower technology nodes. The candidate should be able to drive all aspects of physical design tasks on SOC solutions technologies for next generation client processor chip. Direct Responsibilities: Full chip, subsystem and partition level floorplanning, physical design, physical verification of SOC. Responsible for partition and/or top level clocking, power grid routing; pin placement, memory placement in blocks. Own or work with full chip and block static timing engineers to close timing .Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC physical design flow: synthesis, full chip and block floorplanning, place and route, timing and power to create a design database that is ready for manufacturing. The ideal candidate will be able to demonstrate the following behaviors: Ability to work effectively with both internal and external teams/customers is expected. Ability to mentor other engineers and technically guide them. Experience with silicon which include processor cores and custom logic working together. Strong problem solving skills Strong written and verbal communication skills. Capable of working in a high performing team to deliver the results required from the organization. Facilitator of direct and open communication, diversity of opinion, and debate. Experience in people, project management and organization skillsQualificationsEducation: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 10+ years of experience Key skills: Experience in physical implementation with multiple design cycles in ASIC flow is required. Strong knowledge of synthesis, physical design, STA and verification flows, methodology and knowledge of all aspects of physical design is required. Experienced in industry standard tools such as, Synopsys ICC/ ICC2, Innovus PrimeTime, ICV, Mentor Calibre, and Calibre DRV is required. Experience in scripting languages, preferably Perl, Python, Tcl, etc.is preferred. Excellent oral and written communication skills. Experience in project management skillsInside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intels leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0151910Bangalore,

Keyskills :
drawingautocaddraftingmodelingcadphysical designorganization skillsverbal communicationphysical verificationwritten communicationsocstatclips