SoC DFT Engineer

Job Description

Job ID: JR*******Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSoC DFT EngineerJob DescriptionThe Xeon Server Solutions(XSS) Group is searching for an energetic, passionate and process oriented DFx engineers who has extensive experience in implementation and verification of DFx features for multiple SoCs. We are looking for someone who has passion around improving the way we solve complex problems through team work as well as their own direct contributions. Direct Responsibilities: In this role you will be responsible for working with stakeholders to implement and verify Memory DFT features in pre silicon as well as supporting silicon validation for leading edge SoC designs. Includes responsibility for supporting manufacturing and testability of our products, design; verification using Memory test tools for pattern generation and coverage, debug, scan synthesis, Test Mode STA and gate level simulation. Experience in Mentor MBIST solutions , JTAG ( 1149.1, 1149.6 ; 1149.7) , IJTAG ( 1687), BScan design implementation and verification will be added advantage. Responsibilities include delivery of high-quality documentation for consumption by the post-silicon teams using the DFx features. The ideal candidate will be able to demonstrate the following behaviors: Ability to work effectively with both internal and external teams. Ability to mentor other engineers and technically guide them. Strong problem-solving skills. Strong written and verbal communication skills. Facilitator of direct and open communication, diversity of opinion, and debate.QualificationsBS degree in Electrical Engineering Computer Engineering or other related field of study with a minimum of 7+ years or MS degree with 5+ years of directly related industry experience in SOCIP DFx Design and Verification. Candidates must have the following Proven expertise in Silicon product development. Experience in development of Memory test implementation, RTL coding and validation of IP and SoC. DFx Experience in working closely with physical design team to ensure timing closure for DFx IPSoC logic at full chip RTL design of DFx IP and SoC logic. The ability work as an individual and as part of a team to deliver a product starting from the creation of the spec design and verification. Need a good understanding of System Verilog, scripting languages like shell scripting PERL, sound understanding of test strategies , debug flows , ATPG tools and GLS. Working experience with postsilicon teams to comprehend usage models, test time and tester capabilities. Strong Si debug skills ATE requirements Strong Communications skills and the ability to effectively work with cross functional teamsInside this Business GroupXeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR*******BangaloreXeon Performance Group (XPG),

Keyskills :
atpgdftscancoresiliconcontinuous improvement facilitationrtl designrtl codingdata centermemory testmarket sharesystem verilogtiming closureshell scripting