| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Oil & Gas Jobs |
| Banking Jobs |
| Construction Jobs |
| Top Management Jobs |
| IT - Software Jobs |
| Medical Healthcare Jobs |
| Purchase / Logistics Jobs |
| Sales |
| Ajax Jobs |
| Designing Jobs |
| ASP .NET Jobs |
| Java Jobs |
| MySQL Jobs |
| Sap hr Jobs |
| Software Testing Jobs |
| Html Jobs |
| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Understanding of Scan/MBIST RTL architecture, scan design and methodology to deliver scan enabled netlist (scan synthesis).Analyze netlists for scan insertion & MBIST design to meet coverage goals and providing feedback for coverage improvement.Perform scan coverage analysis and debug with Spyglass-DFT or other ATPG tools.Scan RTL and GLS test validation to ensure scan quality design deliverables.Creates, simulates and verifies automatic generated test patterns (ATPG) using industry standard tools, analyze and drive the improvements to test coverage.Coordination of Scan/ATPG collaterals with IP provider.Deliver validated scan & MBIST patterns to post-Silicon High Volume Manufacturing (HVM) partner teams for silicon testing usage.Partnership with post-Silicon High Volume Manufacturing (HVM) Team to enable MBIST & Scan DFT test capability in silicon.Support debug of any test content failures in the post-Silicon/HVM environment.QualificationsBachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of experience. Knowledge in scan RTL integration and scan validation methodologies. Experience in implementing scan DFT/Test in designs. Understanding of DFT Infra, scan insertion, scan stitching, Scan/ATPG collaterals, ATPG process, scan compression, scan synthesis & scan timing . Familiar with Scan design, methodology, coverage analysis and test validation. Experience in software/scripting proficiency (Perl, C++, or equivalent) to automate design process and improve efficiency. Familiar with UNIX, and well-versed in Verilog/System Verilog. Independent problem solving, debugging various simulation failures, formal verification etc. Ability to communicate well with counterparts and key stakeholders including cross-site partners.Inside this Business GroupThe Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intels leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.,
Keyskills :
drawingautocaddraftingmodelingcadcontinuous improvement facilitationscan insertionproblem solvingtest validationbehavioral trainingformal verification