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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | Service / Installation / Repair |
| EmploymentType | Full-time |
Thorough knowledge of the ASIC design timing closure flow and methodology. Expertise in STA tools (Primetime/Tempus) and flow. Knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints debug. Proficient in scripting languages (TCL). Familiarity with backend related methodology and tools. Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired. Strong background in Constraint analysis and debug Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing. Self-starter and highly motivatedLocation 1.Bangalore &2.HyderabadNotice period up to 30 daysApply Now,
Keyskills :
asic designtiming closuresignal integritymaxstabistscanertmsdesignsalarytimingbackendclosuremergingembeddedanalysisscriptingRTL Designasic