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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Rs 1.0 - 5 Lakh/Yr |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Essential Duties And Responsibilities: In this position, the individual will be responsible for complete ownership of full chip Synthesis /STA environment for low power, high performance designs, development-debug of interface and core side constraints, clock tree analysis and assisting full chip timing convergence and timing closure. Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments. He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises. The individual will influence next generation synthesis and physical design implementation capability to meet the demands of the ASIC design road map. Ability to work with minimal supervision and drive to exceed expectations is a plus. Hands on direct experience in Synthesis with emphasis on STA and Low Power design. Proficiency in understanding and writing Verilog, System Verilog RTL, STA closure and experience in PERL/TCL/Shell scripting is a must. The individual must have proven hands on experience on multiple low power hierarchical and flat ASICs at 28/16nm designs. Expertise in Design Compiler is a must. Experience with DFT Compiler, RTL Compiler and Conformal is a PLUS. Good verbal and written communication skills are required. ,
Keyskills :
asic designrtl compilerdft compilersystem verilogphysical designdesign compilercommunication skillswritten communicationintegration strategiesedadftrtlstaroaddesigntimingwritingverilogasic