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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
The data infrastructure that our customers build has never been more critical to our global economy. It s what s keeping the world connected, businesses running, and information flowing. If you re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The OpportunityRoles and ResponsibilitiesExecute and deliver block/chip level place and route from RTL to GDS for different Marvell BU productsInteract with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goalInteract with design team to understand timing, CTS goals in detail to solve problems and propose physical design ideasDebug timing constraint issues and feedback to design teamDebug LP issues and feedback to design teamSetup and Run physical design steps Floorplan, PG Mesh Creation, Placement, CTS, Routing optimizations to achieve PPA goalCheck Logic equivalence from pre layout to post layout netlistAnalyze timing within PD environment and using STA tools and achieve timing closure by generating and applying ECOs to layoutInteract with PV team to analyze DRC/LVS/ANT/ERC results and achieve PV closureAnalyze results from PGV, fix IR drop issues and achieve closureDevelop perl/tcl scripts for generic tasks as requiredRequired Skills8 to 10 years of experience in block/chip level Physical Design executionGood understanding and hands on experience in physical design tasks Floor-planning, PG mesh creation, placement, CTS and Routing for complex blocksGood knowledge on timing constraints, static timing analysis, debug problems and closureGood knowledge on DRC/LVS/ANT/ERC issues and closureGood knowledge on IR drop, ESD, EM issues and fixesGood knowledge on low power concepts and application to PDExperience with cutting edge technology node designs like 16nm, 12nm, 7nmAbility to plan and work independently and coordinate with cross functional teamsScripting skills using perl/tclGood communication skills and ability work as a teamHands on expertise with industry standard EDA tools including but not limited to Design Compiler/RTL Compiler, Innovus/ICC2, Primetime/Tempus, QRC/StarXT, CalibreEducation Qualification: BE/BTech/ME/MTech/ in E&C, EEE from the reputed institution,
Keyskills :
floor planningdrcroutingverificationstatic timing analysiseda toolstiming closurephysical designtiming analysiscommunication skills