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| Job Location | Bangalore |
| Education | Not Mentioned |
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| EmploymentType | Full-time |
Job ID: JR0185037Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireTFM EngineerJob DescriptionPerforms logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.QualificationsQualification : - Master of Science (or a Master of Technology) degree in Electrical Engineering with more than four years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than six years of relevant industry experience. - Experience : Relevant ASIC design experience - Expertise in verilog and system verilog based logic design - Experience with IP Design Tool Flow methodologies - Strong experience in synthesis and timing closure - Experience in Industry standard tools like Spyglass Lint, Spyglass CDC, DC, LEC - Experience in DFT tools, Simulation tools, VC LP, Fishtail, Power artist - Expert level knowledge of Unix, Perl, Python, Design Compiler, Conformal. - Good understanding of Front-End methodologies - Looking for highly motivated individuals who has passion to solve TFM problems for IPs - Ability to work with EDA vendors to solve Design tool issues.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0185037BangaloreIP Engineering Group (IPG),
Keyskills :
front endasic designlogic designsystem verilogtiming closuredesign compilerbehavioral trainingelectrical engineeringedadftsocrtlleccdctfmperlips