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MTS Physical Design Engineer (Power Optimization)

5.00 to 10.00 Years   Hyderabad   11 Jan, 2022
Advanced Micro Devices, Inc
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryTelecom / ISP
Functional AreaService / Installation / Repair
EmploymentTypeFull-time

Job Description

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.MTS Physical Design (power optimization)THE ROLE:Physical Design s Power is a more and more hot topic in IC Physical design. We are a power/performance/area optimization methodology team. In this position, you will work with global physical design team for GPU chips physical design power optimization/reduction. Focus on physical design methodology optimization/update to improve chip Power and Performance/Area (PPA), including Syn ->place&route iteration/optimizing. The individual is expected to be an expert in physical design areas, it is a plus to have strong ability in multiple aspects in Front-End or RTL coding experience or Synthesis. The individual is expected to know back-end physical design very well, be very familiar with physical design power reduction methodology. THE PERSON:Strong self-motivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit help and support team members.KEY RESPONSIBILITIES:

  • implement state-of-art physical design power optimization methodology into SOC project
  • use, maintain and enhance the power optimization methodology in physical design flow.
  • Closely co-work with SOC project design team, help/support/drive them adopt the physical design power optimization methodology
PREFERRED EXPERIENCE:
  • Preferred 10+ years or more years of experience in physical design in digital ASIC chips
  • Strong PnR, top level floorplan, STA, IR/EM knowledge/experience.
  • Be very familiar with physical design power optimization methodology, (eg. Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-bandking, scan path power )
  • Expert in Back-End (physical design) EDA tools, especially the power calculation/optimization tools, PTPX, Redhawk is a plus.
  • strong flow develop and custom script develop ability
  • Knowledgeable in all aspects of deep submicron ASIC design flow
  • Successfully gone through several complete product development cycles
  • work well with cross-functional teams
  • Good listening, writing and speaking English
  • Good communication skills, strong interpersonal skills and the flexibility
ACADEMIC CREDENTIALS:
  • preferred MSEE with 5+ years or Bachelor with 8+ years of industrial experience in ASIC design
LOCATION:
  • Hyderabad
#LI-AP2Requisition Number: 121662 Country/Region/Location: India State/Province: Telangana City: Hyderabad Job Function: DesignApply nowApply nowApply for JobEnter your email to apply,

Keyskills :
verificationdrceda toolsroutingrtl codingproject designfloor planningchanging the worldasic designteam spiritstrong interpersonal skillsfront end

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