Need now DV Coverage analysis

3.00 to 5.00 Years Bangalore 20 May, 2023

Job Location	Bangalore
Education	Not Mentioned
Salary	Not Disclosed
Industry	IT - Software
Functional Area	Statistics / Analytics
EmploymentType	Full-time

Job Description

ASIC/SOC/IP Verification plan definition, testbench environment development in System Verilog/UVM Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level Support of assertion and coverage-driven methodology Develop test cases to verify functional operation of that the system level. Experience in any of the protocol like PCIe or Ethernet or DDR, or USB. Communicate test progress, test results, and other relevant information to project lead. Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws Code and functional coverage objects of different blocks. Key Skills: ASIC/SOC/IP Verification plan definition, testbench environment development in System Verilog/UVM Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level Support of assertion and coverage-driven methodology Develop test cases to verify functional operation of that the system level. Experience in any of the protocol like PCIe or Ethernet or DDR, or USB. Communicate test progress, test results, and other relevant information to project lead. Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws Code and functional coverage objects of different blocks.,

Keyskills :
test casesddrpcieobjectsanalysisethernetprotocolTest Strategy

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Need now DV Coverage analysis

Job Description

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