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Module Lead/Lead Engineer - FPGA Verification

4.00 to 5.00 Years   Gurugram   05 Mar, 2021
Job LocationGurugram
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Hardware / Networking
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Since 1992, Ciena has been driven by a relentless pursuit of network innovation. We believe in a network that grows smarter, more agile, and more responsive every day. This means that when you digitally interact in your world - picking up the phone, streaming video, texting a friend or loved one your interactions are being enabled by Ciena technologies. Ciena makes your social / entertainment / business existence REAL.What will you do at CienaHigh speed FPGA logic design, for Packet networking hardware of Ethernet, IP/MPLS, and IP OAM and SAT (Service Activation Testing) protocols, statistics, packet timing, TDM circuit emulation, as well as, system glue logic for packet access switching and routing platforms.ESSENTIAL DUTIES AND RESPONSIBILITIES

  • Develop complex FPGA logic architecture, code, simulation, and Verification.
  • Hands on bench testing of new designs for compliance to design specifications.
  • Complete documentation throughout design and development cycle from theory of operation to test specifications
  • Responsible for communication and coordination with Software, Hardware, System Engineering and Validation, teams throughout the design and development cycle
  • Coordinate with technical team members design reviews, feature specifications, etc.
  • Attend meetings, report progress, and take technical leadership to troubleshoot and fix defects.
  • Provide guidance and mentoring for junior engineers hired into the team who may be tasked to perform some of the above duties.
  • Help investigate and collect information to resolve process or design issues found on a current design or in previous designs.
  • Assumes other duties as assignedSKILLS
  • High speed FPGA/IP block logic design for Packet Networking equipment.
  • Design of Layer 2 or Layer 3 IP blocks for Ethernet/IP protocols with packet parsing, switching, routing, traffic management, scheduling, shaping, admission control functions in FPGAs or ASICs with 1Gb Ethernet to 400Gb Ethernet/IP designs.
  • Knowledge with industry standards such as IEEE 802.3 standards for 1/10G , 100G Ethernet PCS and MAC layers , OAM , SAT , MEF standards, ITU-T standards, relevant RFCs such as Pseudowires, Ethernet metering etc. 5G Radio fronthaul standards such as RoE(Radio over Ethernet), Open RAN, CPRI/eCPRI standards.
  • FPGA/ASIC front end design using synthesis and simulations tools with System Verilog and/or VHDL.
  • Worked as design lead for full FPGA/ASIC or IP blocks.
  • Timing closure for FPGA or ASICs. Fully aware for timing constraints and methodologies.
  • Keen to develop FPGAs/ASIC blocks with high quality following rigorous quality checklists and methodologies.
  • Experienced with PERL/Python scripting.
  • Block/IP level verification of the same.
  • Validation of such FPGA/ASIC in System towards final deliverables.
  • Strong knowledge of using design tools for analysis, development, testing, and debug.
  • Knowledge and experience designing with Altera/Intel and Xilinx FPGAs with Quartus or Vivado tools.
  • Use of standard bench level test equipment such as oscilloscopes, logic analyzers, and other supporting equipment.
  • Ability to resolve complex issues that may require design trade-offs.
  • Excellent verbal and written communication skills.
DESIRED CHARACTERISTICS
  • Self-starter with positive attitude
  • Team orientation, organized, and capable of independent work
  • Acumen for problem solving. Ability to lead in an environment of change flexibility, creativity and patience
  • Ability to learn and grasp technical concepts related to products being developed
  • Able to work effectively and communicate at all levels within the Ciena workforce
EDUCATION / EXPERIENCE
  • B.E/BTech in Electronics Engineering and/or M.Tech preferred.
  • Minimum 4 years experience doing FPGA/ASIC design from requirements, using FPGA development tools with Verilog and/or VHDL.
*LI-CNAbout CienaCiena is a network strategy and technology company with a passion to provide an experience, to you and our customers that is as rewarding as the outcome. We attract the best and brightest those with outstanding talent, motivation, and the right attitude to contribute to our success. Our culture balances our openness and informality with professionalism and trust and is built on the foundation of our core values: Customer First, Integrity, Velocity, Innovation, and Outstanding People. Ciena enables everyone to have a voice and a network that supports them while on the journey to discovering their passion and purpose. We trust each individual to do what they can to reach their full potential and make an impact on the business, whenever, wherever they are in the world. With Ciena s highly innovative, forward-thinking business practices, we reward people for pushing the boundaries. Unlock your potential at Ciena!Being You CienaAs part of our commitment to diversity and inclusion, we want to foster an environment that values and respects all individual s strengths, perspectives, ideas, and ability to meet the needs of our customers globally. Ciena values the diversity of its workforce and respects its employees as individuals, regardless of race, ethnicity, religion, gender, age, national origin, disability, sexual orientation, veteran or marital status or any other category protected by applicable law. We do not tolerate any form of discrimination.Ciena is also committed to compliance with all fair employment practices regarding citizenship and immigration status. If contacted in relation to a job opportunity, you should advise Ciena in a timely fashion of the specific accommodation measures required for you to be assessed in a fair and equitable manner. ,

Keyskills :
linuxwork effectivelydevelopment toolscustomer relationsautomationfront endjavalayer 3test equipmentfront end designlayer 2system veriloglogic designieee 8023

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