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RTL Power Methodology Engineer

20.00 to 25.00 Years   Noida   14 Sep, 2021
NXP Semiconductors
Job LocationNoida
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

NXP SemiconductorsN.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020.Scope of Responsibilities:

  • Experienced in ASIC RTL design
  • Proven hands-on experience with SOC Design and IPs design
  • Knowledge and experience with complex SoC designs based on ARM/ARC and hierarchical interconnect.
  • Expertise in Verilog,VHDL and system verilog based logic design
  • Create detailed micro architecture & implement complex IP or sub-system
  • Work with DV team to debug and meet code coverage metrics
  • Experience in all design tools/standards/simulators like Lint, CDC, DC, VCS & UPF
  • Knowledge of interconnect protocols like AMBA is a must
  • Low power UPF/CPF Flow.
  • Assertion based flows.
  • Regression setup, debug of RTL and gate level netlist
  • Strong experience in Logic synthesis, Lint and CDC checks, DFT, constraining, RTL Integration and UPF.
  • RTL design/release flows/infra (LINT, CDC, UPF, IPXACT, CSR .)
  • RTL assertions
  • Block level design, Verilog coding
  • Specification cleanup, e.g. uArch formatting, review, update.
  • Decent working knowledge in general scripting (Perl, Python etc
  • You will work with EDA Vendors to proactively review latest tools and flows offerings in Digital frontend domains, Evaluate latest offerings and benchmark with NXP used tools, flows and methodologies. Needs to drive decision for next set of selections. Work with EDA Vendors to review and resolve blocking issues.
  • You will insure the compliance of your deliveries to NXP design flow, methodologies.
  • You will be an actor of change for deploying new tools.
Specific skills & knowledge:
  • Bachelor or Master in Electronics Engineering and specialization in VLSI domain.
  • Hands on experience in Digital RTL integration, UPF, CDC, RDC, common structure management, timing constraints writing, Power integrity analysis and LEC.
  • Experience in Synopsys and Mentor digital front-end tools. Needs to work with EDA team in reviewing & resolving blocking issues in project
  • Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time
  • Ability to use scripting languages / automation in digital front-end methodology creation and deployment
  • Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player.
  • Excellent communication skills with proven experience in international relationships
,

Keyskills :
front enddesign flowlevel designcode coveragesystem verilogpower integritylogic synthesiscommunication skillstechnical leadershipelectronics engineeringconnectivity solutionscsr

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