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Senior Design Engineer - Physical Design

4.00 to 6.00 Years   Noida   05 Apr, 2021
NXP Semiconductors
Job LocationNoida
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.Key Responsibilities

  • Would be responsible for hands-on physical implementation and timing closure of core platforms and SoCs.
  • Evaluate and deploy the evolving physical design methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules
  • Active participation in benchmarking of library, technology parameters, implementation strategy to enable design requirements of die size, power & speed.
  • Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure Zero Defect chips
  • Enable technological innovations from day to day learning & project experiences
  • Actively work as part of team both locally & also with remote or multi-site teams
Key Skills
  • Self starter with 2-12 years of experience on SOC/Chip level/IP physical design on multimillion Gate and complex design with multiple clocks and power domains with minimal supervision.
  • Expertise in physical implementation & timing closure flow with hands-on experience in synthesis, formal equivalence, placement, optimization, low power checks, clock tree, routing, crosstalk delay/noise analysis & repair using Cadence/Synopsys/Magma tools.
  • Expertise in clock tree closure from Frequency/Power/EMC/Reliability perspective.
  • Sound knowledge of electrical as well as physical constraints/rules is desired (Physical integration including floor-planning, padring integration, power grid, Power/IR analysis, reliability).
  • Good control over scripting languages like PERL/TCL is MUST.
  • Knowledge of commonly used clocking, low power schemes, spice simulations, DFT techniques are added advantage.
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Keyskills :
autocadcaddrawingmodelingmechanicaltiming closurephysical designquality adherencecontrolled impedanceoptimization strategiesdftiotnxpspicedesignconnectivity solutions

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