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| Job Location | Pune |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Experience: 4 to 7 YearsSkills required:In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. Must have hands-on experience on PnR Suite from Synopsys/Cadence (Innovus, ICC2) Strong experience on Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements. Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.Skills & ExperienceASIC physical design using industry Cadence or Synopsys tools, Full chip and Block level physical design implentation, Physical DesignCyient is an Equal Opportunity Employer.Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.,
Keyskills :
physical designfloor planningsynopsys toolsverificationtiming analysisdrcroutingstatic timing analysishigh speed designadvanced analyticspower integrity