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Senior Staff Engineer - Design Verification

15.00 to 17.00 Years   Pune   05 Jul, 2021
Marvell India Pvt Ltd
Job LocationPune
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaEngineering Design / Construction
EmploymentTypeFull-time

Job Description

The data infrastructure that our customers build has never been more critical to our global economy. It s what s keeping the world connected, businesses running, and information flowing. If you re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The OpportunityAbout MarvellMarvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system-level knowledge, Marvells infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow.At Marvell, you ll see your ideas put to work, share in the success of our company, and achieve a healthy life-work balance in a strong culture of corporate citizenship and global semiconductor leadership. If you are ready to excel, innovate, and truly enjoy where you work, apply now for the position detailed below.The OpportunityInfrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform.Today, Marvell-powered 3/4G solutions provide cellular coverage to over a billion people worldwide. In 5G, Marvell offers complete silicon platforms that enable all aspects of the digital processing domain. Marvell is leveraging decades of integration expertise with an unparalleled portfolio of baseband DSPs, Arm multi-core SoCs, purpose-built hardware accelerators, Ethernet connectivity engines and system-level security solutions.Roles & Responsibility

  • Architect and implement simulation test bench in UVM.
  • Develop and execute test-plans for verifying correctness and performance of the design.
  • Own and debug failures in simulation to root-cause problems
  • Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
Requirements
  • Strong background in Soc verification methodology and test bench development using HVL such as Verilog, System Verilog, UVM and C/C.
  • Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations).
  • Knowledge of Unix/Linux environment and scripting (shell/Perl/Python) is a plus.
  • Demonstrates good analysis and problem-solving skills.
  • Must have the ability to multi-task in a fast paced environment.
  • Must have effective interpersonal and teamwork skills and excellent communication skills.
  • Ability to interface internally and externally with all levels of the organization.
  • Participate in problem solving and quality improvement activities.
  • BS in CS/EE with 15 years of relevant experience.
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Keyskills :
customer supportdeliveryscrum mastersoftware developmentaccountabilityopen sourcesystem verilogcloud computingproblem solvingsoc verification

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