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Job Location | Delhi |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Define and develop new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation.
Create emulation models from RTL/Netlist.
Develop hardware collateral to be integrated with the Palladium/FPGA emulation model.
Create and execute Test plans targeting Sub-systems and SoC level.
System level performance analysis, bandwidth, latency across interconnect.
Experience with Speed Bridge Integration and perform real time testing.
Experience in integrating Acceleration VIPs and perform co-emulation.
Experience in Palladium or Zebu Platforms
Automate and increase process efficiency
,Keyskills :
process efficiencyperformance analysissocrtlfpgabridgetestingsiliconhardwareanalysisusabilitybandwidthpalladiumemulationvalidationcollateralperformanceintegrationaccelerationBusiness Process Efficiency