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Package Design Engineer 2

4.00 to 6.00 Years   Hyderabad   20 May, 2021
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Description

Master s/Bachelor s Degree in Electrical/Electronic engineering with 4-6 years of experience in package design and layout of advanced and heterogeneous packages to meet/exceed package and system electrical and thermal performances. Successful candidate would be responsible to develop new package solutions including pin-out definitions, DRD/DFM and stack-up requirements. You should also be well versed with chip-package design flow and LVS verification. This job requires excellent communication, teamwork and strong problem solving skills. You will be part of fullchip integration team in Hyderabad, responsible for integration of advanced process node chiplets using InFO technology.

Job Requirements:

  • Experience in CADENCE Allegro Package Designer, including constraints setup
  • Familiarity with AutoCAD, Gerber/ODB++/GDSII conversion software, and DFM tools
  • Strong knowledge in packaging substrate structures and manufacturing
  • Knowledge in 2.5D/3D, flipchip, WLP and wirebond assembly and reliability
  • Knowledge in SPICE, signal/power integrity, DDR3/4, and SerDes channel modeling for high speed design
  • Strong problem solving & excellent communication skills.
  • Exposure to INFO package design and IC design flows are desired.

Education Requirements B.Tech/M.Tech

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Keyskills :
drawingautocaddraftingmodelingcadhigh speed designcontinuous improvement facilitationic designfpga designdesign flowproblem solvingcadence allegropackaging designcommercial modelsdfmlvsfpgaspicedesignxilinx

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