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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
JD for the Role- RTL Design (Emulation experience needed)Experience: 3 + Years, Location: HyderabadBelow is the job description:Tasks & Responsibilities: Minimum of 5 experience in RTL Logic design. RTL Integration experience at Subsystems/ SoC Candidate should have Worked on RTL Lint, Lintra or Spyglass- Lint design flows Required Experience on CDC analysis. Required Experience on Febe flow (Design Compiler, fev) For Logic handoff to Backend team Should have Worked on UPF, Spyglass- LP design flowsAreas of interest are (expertize in any one of them): Domain (a): RTL design for digital signal processing logic design (in Verilog), like filter, fft, matrix operations, control, etc. Domain (b): FPGA, Ethernet packet processing (hardware acceleration), (de- )packetizing modem data for e- CPRI. Upload your CV/ resume or any other relevant file. Max. file size: 128 MB.,
Keyskills :
digital signal processingrtl designlogic designsignal processingsocrtlcdcupffftfpgalintertmsdesignmatrixresumebackendverilogcontrolhardware