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Senior Manager - Physical Design

10.00 to 15.00 Years   Hyderabad   16 Mar, 2024
IDESLABS PRIVATE LIMITED
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT Services & Consulting
Functional AreaNot Mentioned
EmploymentTypeFull-time

Job Description

    HI,Greetings from IDESLABS,This is Swarna, we have immediate requirement on Senior Manager - Physical Design for Fulltime to HIRE for client Capgemini.Job detailsSkillsAbility to lead a team size of minimum of 10 members who can handle Subsystem PNR Subsystem timing closure and Subsystem physical verificationExperience10-15yearsJob LocationBangalore, Hyderabad, Noida, CoimbatoreJob TypeFull TimeInterested candidates share the profile with below detailsSpocshidden_emailhidden_emailhidden_emailhidden_emailCurrent CTCExpected CTCNotice PeriodCurrent LocationDescriptionManage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of. automation scripts. Work with front-end engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting.Desired Skills & Experience Experience level 10 to 15 years. Must possess 10 years of hands on experience in handling block/chip level implementation from Netlist to GDS Must possess hands on experience in timing closure and physical verification closure Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz Experience in handling lower tech nodes that include 40nm, 28nm or lesser nodes etc. Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter or mentor tools. Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time Must possess excellent scripting skills TCL or Perl Experience in Synthesis and Formal is a plus Excellent verbal and written communication skills are required. Must possess excellent debug skills, analytical skills and the ability to work independently. Must be highly motivated and possess excellent team spiritEducation: UG - B.Tech/B.E. Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E, Electrical, Electronics/Telecommunication)Primary SkillsAbility to lead a team size of minimum of 10 members who can handle Subsystem PNR activities , Subsystem timing closure and Subsystem physical verificationSecondary SkillsKnowledge in Subsystem Synthesis, Subsystem IR drop, Subsystem Lec, Subsystem CLP,

Keyskills :
Physical DesignTeam LeadershipTiming ClosurePhysical VerificationStatic Timing AnalysisFormal VerificationPower AnalysisFloorplanningPerlSynthesisSubsystem PNRPlaceandRouteTapeout

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