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Senior Mixed-signal IP Verification Engineer

5.00 to 8.00 Years   Hyderabad   28 Jan, 2021
Xilinx India Technology Services Pvt Ltd
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaNetwork / System Administration
EmploymentTypeFull-time

Job Description

The Product Verification team is looking for a Senior Mixed-signal IP Verification Engineer to join exciting career on functional test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The candidate will work on complex SoC design with multiple mixed-signal IPs, advanced ARM/Microblaze processors, high-speed communication interfaces, DDR memory, programmable logic FPGA and more. Responsibilities:

  • Work closely with IC Design team during pre-silicon verification (chip level verification) and post silicon validation
  • Develop high coverage functional BIST/Firmware driven patterns to test High Bandwidth Memory and PHY
  • Fault Grade and analyse functional test patterns to ensure highest quality
  • Work with Product Engineer to address Yield, Design & Quality issues during New Product Introduction phase and address any post-production issues
  • Balance Test Time with quality to meet product requirement
  • Bachelor/Master degree in Electrical/Electronic Engineering
  • 5-8 years of experience in RTL design and/or HW functional verification
  • Solid understanding of digital/mixed-signal design, static timing analysis and timing closure techniques
  • Fluency in writing synthesizable RTL; Verilog/SystemVerilog
  • Experience in post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
  • Knowledge in DDR4/DDR3 protocol, calibration and training is strongly desirable
  • Experience in using simulation environment for pre-silicon validation is desired
  • Knowledge of advanced processor and embedded C programming
  • Good communication skills, works well in a group environment that spans across continents
,

Keyskills :
verificationuvmdesignfailure analysisstatic timing analysisnew product introductionbig dataic designembedded crtl designtiming closure

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