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Senior Staff Design Engineer

12.00 to 13.00 Years   Hyderabad   11 Jan, 2021
Xilinx India Technology Services Pvt Ltd
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

DescriptionAt Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the worlds first 5G networks, we empower the worlds builders and visionaries whose ideas solve every day problems and improve peoples lives. If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.IPSE Groups:Role is open in IPSE Physical Design group which is responsible for Physical Design (RTL to GDS) of all IP Subsystems like

  • ARM based Multi-Core Processing subsystems, Safety Processing Subsystems, Platform controllers,
  • HBM, DDR5, PCIE, Hardware Accelerators, AI Engine subsystem with more than 500cores, NOC etc.
  • Apart from IP & Sub-systems, new technology exploration like 3Chips, improving Physical Design methodology etc are the key ownership activities of the team.
  • Every IP has it own challenges be it execution, area, low-power, performance, 7nm technology etc.
  • The Role defines the implementation methodology, schedule, plan, Assign, delegate, track and lead the delivery.
We are looking for talented SOC/IP design Physical Design Lead/Manager to join our team and be responsible for :
  • Physical Design (RTL to GDS) of one or multiple IPSE projects,
  • Building, mentoring and leading a design team,
  • Direct interactions with various teams like ARCH, RTL, DFX, AnalogIP, Integration, Silicon Validation etc,
  • Understand the requirements, negotiate, define solutions and decision making for a better efficient designs,
  • Define Design Implementation Methodology, Schedule, Assign, Track, and be responsible for Designs within the group.
  • Involves 70% of Time on Technical Management and 30% on Team Management.
Masters/Bachelors degree in Electrical/ Electronic Engineering with 12+ years of experience in ASIC Design.
  • Very strong knowledge of Physical design concepts (Syn, Floorplan, PG, PnR, PDV, Timing, Signoff).
  • Ability to work as part of a team, train and lead the team with technical direction.
  • Solves technical problems of advanced complexity and conveys/applies solutions
  • Ability to be agile and make progress during critical situations
  • Excellent leadership, communication, negotiation and time management skills
  • Ambitious and ability to motivate a team under critical situations.
  • Good knowledge of scripting and proficient with Industry EDA tools from SNPS and CDN.
,

Keyskills :
adcartcalibrationcmosdacbig dataeda toolsphysical designtime managementsilicon validationtechnical managementcommunity engagementimplementation methodology

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