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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | IT Operations / EDP / MIS,Web / Mobile Technologies |
| EmploymentType | Full-time |
Should lead a team of STA engineers through MMMC Timing signoff for multiple tapeouts of hierarchical designs in 28nm & lower tech nodes. Should have ownership of STA methodology development.Expected to own Timing at SoC level from Synthesis to tapeout, including constraints generation, validation, generating timing budgets, noise analysis, ECO generation & implementation & Timing signoff. Must have handled designs with >1.5GHz clock freq, and be familiar with SoC level timing budgeting flow. Expected to drive STA team to achieve better ECO implementation TAT. Should be a strong team player, with good leadership skills. MandatorySkills: Experience in synthesis of complex SoCs block/top level and writing timing constraints Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints Experience in post-layout STA closure and timing ECOs Worked in technology nodes 45nm and below Knowledge of low-power aware implementation is a plus Tools: RTL Compiler, LEC, CLP, ETS/PTSI/GTExperience (In Month): 72Qualification: B.E/B.Tech,
Keyskills :
javaenvironmentsql serversqlcustomer relationsrtl compilerformal verification