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ENGR II, DESIGN_TL

0.00 to 2.00 Years   Chennai, Hyderabad, Kolkata   14 Mar, 2022
Job LocationChennai, Hyderabad, Kolkata
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    *Skill : ASIC Verification Engineer Experience : 01-03 YrsResponsibilities :Testbench development using System Verilog and UVM Create Verification plans required for the project. Knowledge of C/C++ is advantage Leveraging existing test benches, methodologies and industry best known practices Handle block/Module/IP level verification independently. Create various verification components in SystemVerilog and using related methodology guidelines Debug issues and present / discuss problems with designers independently Run regression, analysis reports, achieve code coverage and functional coverage goals Run netlist verification without and with SDFThanks & Regards,, *Candidate should have a BS or MS in Electrical Engineering with 0-2 years of relevant experience in the areas of ASIC Verifiction, UVM, System Verilog. Job will require ensuring timely execution

Keyskills :
code coveragesystem veriloganalysis reportsasic verificationelectrical engineeringuvmveriloganalysiscomponentsregressionengineeringsystemverilogAssertionsAssertion Based VerificationGcov

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