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ENGR PRIN, DIGITAL

12.00 to 14.00 Years   Chennai, Hyderabad, Kolkata   21 Jun, 2022
ON Semiconductor Technology India Private Limited
Job LocationChennai, Hyderabad, Kolkata
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    *Job Summary:
    • Define and implement block level verification flow, testplans, testbenches and sign-off.
    • Take ownership of functional and code coverage for block level verification.
    • Experience of porting block level verification environment to full-chip/SoC level.
    Responsibilities:
    • Build block level testbench using SystemVerilog and UVM based methodology.
    • Define and implement block level testplan, testbench and testcases.
    • Review and enhance verification methodology for block level verification.
    • Work closely with ASIC design team to build register verification testbench for all chip blocks.
    , *
    • BS in Computer / Electrical Engineering with 12+ years of experience.
    • Must have experience with working on multiple chip verification projects.
    • Hands-on experience with block/Full-chip/SoC level verification using SystemVerilog/UVM.
    • Experience with Ethernet, DDR or PCIe verification is preferable.
    • Experience with 802.11 Wireless MAC is plus.
    • Experience with RTL Verification & Debug tools is plus.
    • Must have good communication skills.

Keyskills :
code coverageddrrtl verificationelectrical engineeringcommunicationasic designdesign

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