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ENGR SR PRIN, DESIGN_TL

8.00 to 13.00 Years   Chennai, Hyderabad, Kolkata   14 Mar, 2022
ON Semiconductor Technology India Private Limited
Job LocationChennai, Hyderabad, Kolkata
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    * A senior principal analog design engineer is expected to quickly take a sub system of analog design through all phases of the design process, including making the architecture of analog sub system, technically managing the team to execute the architecture, design, simulation, and supervision of the layout/verification processes and evaluation/debug of silicon samples. A senior principal Analog IC Design Engineer, will be responsible for entire analog sub systems using CMOS process. That person will manage the team that will work with the latest Cadence analogue design tools (Virtuoso Composer, Verilog) HSPICE and appropriate PC-based tools (Matlab). The nature of the circuits is Mixed Signal involving blocks such as switched capacitor amplifiers, PLL, RAM, hispeed interfaces, references, IO circuits, data converters, and digital building blocks. , * Senior Principal IC Engineer will need to possess a B.E degree and a minimum of 10 years+ experience or M.E and a minimum of 8 years experience in the CMOS, analogue/power/mixed-mode IC design areas using the above tools (or similar).

Keyskills :
ic designmixed signalanalog designramcmosertmsdesignhspicesiliconanaloguecircuitssimulationinterfacesamplifierssupervisionarchitectureBiCMOScadenceLowpower Design

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